RF Board—OXG-SDR4100
● Xilinx Zynq SOC FPGA
●Cortex A9 dual core processer
●Flexible Data Channel Caching Mechanism
●PCIE2.0 x8，enabling direct interconnection with PCs
●Multiple clock connection modes, facilitating the implementation of large-scale MIMO systems
●Supports PPS and Trigger input and output
●Reference input and output
Auto Phase Calibration and Clock Synchronization
The phase error of each channel is within 1 degree after calibration, which meets the application requirements of both communication and radar systems simultaneously. In addition, the clock distributor supports the cascading of multiple devices, enabling the construction of a large-scale 256×256 MIMO array.
Maximum RF Channel Count
Each device supports 4 transmit channels and 4 receive channels, making it the product with the highest channel density among commercial SDR devices on the current market.
Block Diagram
| Ordering Model | OXG-SDR4100 |
| RF Section Technical Specifications | |
| RF Channels | 4 Transmit, 4 Receive |
| Transmit Power | ≥ 10 dBm per channel |
| Supported Frequency Band | 300MHz～6GHz |
| Signal Bandwidth | 100MHz |
| Transmit Frequency Error | ±1ppm |
| Transmit EVM | 3%，typical value:5dBm @20MHz bandwidth |
| High-Speed ADC | 16bit, 4-channel |
| High-Speed DAC | 14bit，4-channel |
| Clock Stability | ±1ppm |
| Baseband Section Technical Specifications | |
| Data Processing Unit | ≥ XILINX ZYNQ SoC FPGA 7Z100 |
| PL DDR3 SDRAM | ≥1GB |
| PS DDR3 SDRAM | ≥512MB |
| Data Interface | PCIE 2.0， 8x |
| Synchronization Interface | Supports external reference clock input/output and GPS expansion interface |
| Debug Interface | USB JTAGInterface |
| Dimensions | Standard full-height, 3/4-length PCIe card |
| Wireless Communication Protocol Stack | |
| Supports open-source OAI 5G protocol stack and provides reference design code for gNodeB and UE | |
Specifications and Characteristics
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PRODUCT
Block Diagram
